The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to enhancing speed and reducing the amount of programmable space used by arbitration logic in an integrated circuit (e.g., an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Additionally, FPGAs may include input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may support various communication protocols and may include high-speed transceiver channels through which the FPGA may transmit serial data to and/or receive serial data from circuitry that is external to the FPGA.
In network or bus topologies, components receiving commands (e.g., requests) from multiple masters may utilize arbitration to grant access to only a single master data payload at a time. Accordingly, an FPGA may include an arbitration scheme that provides shared access of the component with multiple masters. However, such arbitration schemes may utilize a significant portion of the FPGA programmable logic. Further many arbitration schemes cannot be sub-divided, causing the arbitration schemes to be on the critical path of many FPGA designs, often being a bottle-neck. Thus, current arbitration schemes of FPGAs are problematic, making it challenging for FPGAs to achieve improved system on chip design performance.